butterfly computation meaning in English

蝶形计算

The key to the fft algorithm is the design of butterfly computation and that of the address logic . the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ) , basing on these , we do our research on reconfigurable technology . the result indicates that the data processing ability of reconfigurable system improved greatly
结果表明，可重构系统在数据处理能力方面比以往的系统有了很大的提高，本设计实现的fft重构处理器可工作于60mhz下，完成一个16点fft需要132个主时钟周期，完成32点fft需要324个主时钟周期，而且具有一定可重构性，可以方便地将其运算点数进行扩展，或将其他的图像处理算法在实时处理系统中实现。